This application relates generally to packet-based networks, and, more particularly, to processing parallel input data using feedback in packet-based networks.
Processor-based systems from personal computers to mainframes may include a wide variety of components that are interconnected using cabling, buses, bridges, or other networking elements such as routers, repeaters, or switches. The interconnections may be used to form packet-based networks of processor-based systems such as wide area networks (WANs), local area networks (LANs), and the like. For example, processor-based systems or logic circuits within the systems may exchange packets of data over an Ethernet, which is a family of computer networking technologies for LANs. Ethernet was commercially introduced in 1980 and standardized in 1985 as IEEE 802.3. The Ethernet standards support several wiring and signaling variants of the Open Systems Interconnection (OSI) physical layer. The original 10BASE5 Ethernet used coaxial cable as a shared medium. Later versions of Ethernet use twisted pair and fiber optic links in conjunction with hubs or switches as the shared medium. Data packets transmitted on an Ethernet may be called Ethernet frames. Each packet or frame includes source and destination addresses and error-checking data so that damaged data can be detected and re-transmitted.
Packet-based networks may also transmit packets or frames according to other protocols. For example, packet-based networks may exchange packets or frames using the Generic Framing Procedure (GFP) defined by the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.7041. For another example, packet-based networks may exchange packets or frames using the 10 Gbit/s Ethernet Passive Optical Network (10G-EPON) standard that supports data transmission in two configurations: a symmetric configuration that operates at a data rate of 10 Gbit/s in the upstream (customer-to-provider) and downstream (provider-to-customer) directions and an asymmetric configuration that operates at 10 Gbit/s in the downstream direction and 1 Gbit/s in the upstream direction. The 10G-EPON standard was ratified as IEEE 802.3av standard in 2009.
Data transmission rates have steadily increased and are expected to continue to increase. For example, early versions of Ethernet transmitted data at a maximum rate of approximately 10 Mbps and subsequent versions increased the data transmission rate from 100 Mbps to the current maximum data rate of 100 Gbps. Limitations on the clock frequency used for the data transfer result in a corresponding increase in the width of the parallel data paths used to carry the transmitted data. For example, a parallel input data path to an FPGA circuit that uses a 125 MHz clock frequency needs to be eight bits wide to support a data transfer rate of 1 Gbps=8×125 MHz. Further increases in the data transfer rate would require increases in either the clock frequency or the width of the parallel data path. In cases where the maximum clock frequency is limited, such as FPGA circuits, the only way to increase the data transfer rate is to increase the width of the parallel data path.
Logic functions along the data path may compute output values using input data values and feedback from entities further along the data path. The logic function may be required to process the input values and the feedback in a single clock cycle. For example, error checking or correction can be performed using a cyclic redundancy check (CRC) calculation that is performed using input data for the current clock cycle and previous values of the CRC calculation. The previous CRC values may be stored in a register that is downstream from the logic that calculates the CRC value. Consequently, the CRC logic should perform the CRC calculation and store the output value in a register in a single cycle so that the output value of the CRC can be fed back and used to compute the CRC value for the next clock cycle. For another example, frames that use the GFP standard may include a frame check sequence (FCS) that includes extra checksum characters for error detection. For yet another example, the 10G-EPON standard employs a stream-based forward error correction (FEC) mechanism based on Reed-Solomon coding for upstream and downstream channels in the symmetric configuration and downstream channels in the asymmetric configuration. Upstream channels in the asymmetric EPON may use an optional frame-based FEC using Reed-Solomon coding.